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order number: 315514-002 revision 2.5 82573 family of gbe controllers datasheet product features ? pcie* ? x1 pcie* interface on ich7 or mch devices ? peak bandwidth: 2 gb/s per direction ? power management ? high bandwidth density per pin ? mac ? optimized transmit and receive queues ? ieee 802.3x compliant flow control with software controlled pause times and threshold values ? caches up to 64 packet descriptors per queue ? programmable host memory receive buffers (256 bytes to 16 kb) and cache line size (16 bytes to 256 bytes) ? 32 kb configurable transmit and receive fifo buffer ? mechanism available for reducing interrupts generated by transmit and receive operation ? descriptor ring management hardware for transmit and receive ? optimized descriptor fetching and write-back mechanisms ? wide, pipelined internal data path architecture ? phy ? integrated phy for 10/100/1000 mb/s full and half duplex operation ? ieee 802.3ab auto negotiation support ? ieee 802.3ab phy compliance and compatibility ? dsp architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation ? host offloading ? transmit and receive ip, tcp and udp checksum off-loading capabilities ? transmit tcp segmentation, ipv6 offloading, and advanced packet filtering ? ieee 802.1q vlan support with vlan tag insertion, stripping and packet filtering for up to 4096 vlan tags ? descriptor ring management hardware for transmit and receive ? manageability ? intel? active management technology (intel? amt) support (82573e only) ? alerting standards format 2.0 and advanced pass through support (82573e/v only) ? boot rom preboot execution environment (pxe) flash interface support ? compliance with pci power management 1.1 and advanced configuration and power interface (acpi) 2.0 register set compliant ? wake on lan support ? additional ? three activity and link indication outputs that directly drive leds ? programmable leds ? internal pll for clock generation that can use a 25 mhz crystal ? power saving feature for the 82573l. during the l1 and l2 link states, the 82573l asserts the clock request signal (clkreq#) to indicate that its pcie* reference clock can be gated ? on-chip power control circuitry ? loopback capabilities ? jtag (ieee 1149.1) test access port (tap) built in silicon ? technology ? lead-free 196-pin thin and fine pitch ball grid array (tf-bga) package ? operating temperature: 0 c to 70 c (with external regulators) ? operating temperature: 0 to 55 c (with on- die 2.5v regulator) ? storage temperature -40 c to 125 c
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3 datasheet?82573 contents 1.0 introduction .............................................................................................................. 7 1.1 document scope ................................................................................................. 8 1.2 reference documents .......................................................................................... 8 1.3 82573 architecture ............................................................................................. 9 1.4 product codes for the 82573............................................................................... 10 2.0 signal descriptions .................................................................................................. 10 2.1 signal type definitions....................................................................................... 10 2.2 pcie* data signals ............................................................................................ 11 2.3 pcie* miscellaneous signals ............................................................................... 11 2.4 non-volatile memory interface signals ................................................................. 12 2.5 miscellaneous signals ........................................................................................ 12 2.5.1 reset and power-down signals................................................................. 12 2.5.2 system management bus (smbus) signals................................................. 13 2.5.3 led signals ........................................................................................... 13 2.5.4 other signals......................................................................................... 13 2.6 phy analog and crystal signals ........................................................................... 14 2.7 test signals...................................................................................................... 15 2.7.1 mac test signals.................................................................................... 15 2.7.2 phy test signals .................................................................................... 15 2.7.3 other test signals .................................................................................. 15 2.8 power signals ................................................................................................... 16 2.8.1 power support signals ............................................................................ 16 2.8.2 digital and analog power supply signals ................................................... 16 2.9 grounds and no connects .................................................................................. 16 3.0 voltage, temperature, and timing specifications .................................................... 17 3.1 absolute maximum ratings ................................................................................. 17 3.2 recommended operating conditions .................................................................... 17 3.3 power supply connections .................................................................................. 17 3.3.1 external lvr power delivery .................................................................... 18 3.3.2 power sequencing with external regulators ............................................... 19 3.3.3 internally generated power delivery ......................................................... 20 3.3.4 internal lvr power sequencing ................................................................ 21 3.4 dc and ac specifications.................................................................................... 25 3.5 external interfaces ............................................................................................ 28 3.5.1 crystal.................................................................................................. 28 3.5.2 external clock oscillator ......................................................................... 28 3.5.3 non-volatile memory (nvm) interface: eeprom ......................................... 29 4.0 package and pinout information ............................................................................. 30 4.1 package information.......................................................................................... 30 4.2 thermal specifications ....................................................................................... 32 4.3 pinout information ............................................................................................ 33 4.3.1 pcie bus interface signals....................................................................... 33 4.3.2 non-volatile memory interface signals ...................................................... 34 4.3.3 miscellaneous signals ............................................................................. 34 4.3.4 phy signals ........................................................................................... 35 4.3.5 test signals........................................................................................... 35 4.3.6 power supply signals.............................................................................. 36 4.4 visual pin assignments....................................................................................... 38
82573?datasheet 4 figures 1 82573 block diagram................................................................................................. 9 2 minimum requirements for power supply sequencing ...................................................20 3 power supply sequencing ..........................................................................................21 4 82573 2.5v and 1.2v lvr schematic ..........................................................................25 5 external clock oscillator connectivity to the 82573 .......................................................29 6 82573 controller tf-bga package ball pad dimensions..................................................30 7 82573 mechanical specifications .................................................................................31 8 82573e and 82573v gigabit ethernet controller pinout..................................................38 9 82573l gigabit ethernet controller pinout....................................................................39
5 datasheet?82573 tables 1 absolute maximum ratings ....................................................................................... 17 2 recommended operating conditions........................................................................... 17 3 3.3v external supply voltage ramp and sequencing recommendations .......................... 18 4 2.5v external supply voltage ramp and sequencing recommendations .......................... 18 5 1.2v external supply voltage ramp and sequencing recommendations .......................... 19 6 3.3v internal power supply parameters ...................................................................... 20 7 82573 bill of materials (bom) of components for internal regulator................................ 22 8 2.5v internal lvr specification .................................................................................. 22 9 1.2v internal lvr specification .................................................................................. 23 10 pnp specification ..................................................................................................... 23 11 82573e and 82573v maximum measured external power characteristics ......................... 25 12 82573e and 82573v typical measured external power characteristics ............................. 26 13 82573e and 82573v 2.5v internal power regulator numbers......................................... 26 14 82573l maximum measured power characteristics ....................................................... 27 15 82573l measured power characteristics ...................................................................... 27 16 dc specifications ..................................................................................................... 27 17 led dc specifications............................................................................................... 28 18 crystal specifications................................................................................................ 28 19 specification for external clock oscillator .................................................................... 29 20 nvm interface timing specifications for eeprom .......................................................... 29 21 thermal resistance values ........................................................................................ 33 22 pcie data signals .................................................................................................... 33 23 pci express miscellaneous signals .............................................................................. 34 24 non-volatile memory interface signals........................................................................ 34 25 reset and power-down signals .................................................................................. 34 26 smbus signals ......................................................................................................... 34 27 led signals............................................................................................................. 34 28 other signals .......................................................................................................... 34 29 analog and crystal signals ........................................................................................ 35 30 82573e/v mac test signals....................................................................................... 35 31 82573l mac test signals .......................................................................................... 35 32 phy test interface signals ........................................................................................ 35 33 82573e/v other test signals ..................................................................................... 36 34 power support signals .............................................................................................. 36 35 power signals.......................................................................................................... 36 36 ground signals ........................................................................................................ 37 37 82573e/v no connect signals.................................................................................... 37 38 82573l no connect signals ....................................................................................... 37
82573?datasheet 6 revision history date revision description jan 2007 2.5 updated the phy_ref signal description in section 2.6. oct 2006 2.4 added document order number. corrected the aux_pwr pin (c6) description for the 82573e/v. updated table 18 ?crystal specifications?. updated the visual pin assignments for the 82573l. major edit all sections. august 2006 2.3 chapter 1, introduction, corrected note. 3.5.1, removed line item 3.5.2, corrected title heading june 2006 2.2 revised section 3.3, ?pcie miscellaneous signals" , updated intel logo. feb 2006 2.1 added section 5.2, ?thermal specifications" .? sept 2005 2.0 integrated 82573l information into this document. june 2005 1.5 initial public release.
7 datasheet?82573 1.0 introduction note: unless specifically noted, 82573 refers to the intel? 82573e, 82573v and 82573l gbe controllers. 82573 gbe controllers are single, compact components with integrated gigabit ethernet media access control (mac) and physical layer (phy) functions. these devices use pcie* architecture (revision 1.0a). for desktop, workstation, and value server network designs with critical space constraints, the 82573 enables a gbe implementation in a very small area. the 82573 provides a standard ieee 802.3 ethernet interface for 1000base-t, 100base-tx, and 10base-t applications (802.3, 802.3u, and 802.3ab, respectively). in addition to managing mac and phy ethernet layer functions, the 82573 manages pcie* packet traffic across its transaction, link, and physical and logical layers. the 82573e contains a dedicated microcontroller for manageability with an on-board intel ? active management technology (intel ? amt) enabling network. this enables manageability implementations required by information technology personnel for out- of-band management, remote troubleshooting and recovery, asset management, and non-volatile storage. intel ? amt is the first step towards a complete intel ? cross- platform manageability program (intel? cpmp), which is a business and technology initiative to deliver consistent management capabilities, protocols, and interfaces across all intel platforms. the 82573e and 82573v gbe controllers have an integrated system management bus (smbus) port enabling industry standards, such as the alert standard forum (asf) 2.0. with smbus, management packets can be routed to or from a management processor. in addition, integrated asf 2.0 circuitry provides alerting and capabilities with standardized interfaces. the 82573 with pcie* architecture is designed for high performance and low memory latency. the device is optimized to connect to a system i/o control hub (ich7) using one pcie* lane. alternatively, the 82573 is able to connect to a memory control hub (mch) device with a pcie* interface. wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. the 82573 efficiently handles packets with minimum latency by combining a parallel and pipelined logic architecture optimized for gbe and independent transmit and receive queues. the 82573 also includes advanced interrupt handling features and uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors per queue cached on chip. a 32-kb on-chip packet buffer maintains superior performance. in addition, using hardware acceleration, the 82573 offloads tasks from the host (for example, tcp/udp/ip checksum calculations and tcp segmentation). the 82573l features low power management. during the l1 and l2 link states, the 82573l asserts the clock request signal (clkreq#) to indicate that its pcie* reference clock can be gated. the 82573 is packaged in a 15 mm x 15 mm, 196-ball grid array (bga).
82573?datasheet 8 1.1 document scope this document contains targeted datasheet specifications for the 82573 gbe controller, including signal descriptions, dc and ac parameters, packaging data, and pinout information. 1.2 reference documents this application assumes that the designer is acquainted with high-speed design and board layout techniques. the following documents provide additional information: ? ieee standard 802.3, 2000 edition. institute of electrical and electronics engineers (ieee). ? pci express base specification, revision 1.0a. pci special interest group. ? pci express card electromechanical specification, revision 1.0a. pci special interest group. ? pci bus power management interface specification, revision 1.1. pci special interest group. ? intel ethernet controller timing device selection guide. intel corporation. ? 82573 nvm map and programming information guide. intel corporation. ? 82573/82562 dual footprint design guide. intel corporation. ? pcie* family of gigabit ethernet controllers software developer?s manual. intel corporation. ? 82573 family gbe controllers specification update. intel corporation.
9 datasheet?82573 1.3 82573 architecture note: the 82573l does not support manageability. figure 1. 82573 block diagram vla n pcie* core nvm slave access logic dma function descriptor management control status logic statistics 32 kb packet ram manage- ability (82573e/ 82573v only) transmit switch receive filters mac phy
82573?datasheet 10 1.4 product codes for the 82573 2.0 signal descriptions 2.1 signal type definitions the signals of the 82573 are electrically defined as follows: device top marking leaded/ unleaded product features 82573e rc82573e leaded 82573e with intel? amt includes: ? intel? amt ?asf 2.0 ?advanced pass through (apt) 82573e pc82573e lead free 82573e with intel? amt includes: ? intel? amt ?asf 2.0 ?apt 82573v rc82573v leaded 82573v baseline includes: ?asf 2.0 ?apt 82573v pc82573v lead free 82573v baseline includes: ?asf 2.0 ?apt 82573l rc82573l leaded 82573l: ? low-power ? no management 82573l pc82573l lead free 82573l: ? low-power ? no management name definition i input standard input only digital signal. o output standard output only digital signal. i/o i/o standard i/o digital signal. ts tr i - st a t e bi-directional three-state digital input/output signal. od open drain wired-or with other agents. the signaling agent asserts the open drain signal, but the signal is returned to the inactive state by a weak pull-up resistor. the pull-up resistor might require two or three clock periods to fully restore the signal to the de-asserted state. a analog pcie, serdes, or phy analog signal. p power power connection, voltage reference, or other reference connection.
11 datasheet?82573 2.2 pcie* data signals 2.3 pcie* miscellaneous signals b input bias pu pull up this signal requires a pull-up resistor. pd pull down this signal requires a pull-down resistor. signal type name and function pe_clkn pe_clkp a(in) pcie differential reference clock the reference clock is furnished by the system and has a 300 ppm frequency tolerance. it is used as reference clock for pcie transmit and receive circuitry and is used by the pcie core pll to generate 125 mhz and 250 mhz clocks for the pcie* core logic. pe_t0n pe_t0p a(0ut) pcie* serial data output these signals connect to corresponding pern and perp signals on a system motherboard or a pcie* connector. series ac coupling capacitors are required at the 82573 device end. the pcie* differential outputs are clocked at 2.5 gb/s. pe_r0n pe_r0p a(in) pcie serial data input these signals connect to corresponding petn and petp signals on a system motherboard or a pcie* connector. the pcie* differential inputs are clocked at 2.5 gb/s. signal type name and function pe_rst# i reset this signal indicates whether or not the pcie* power and clock are available. pe_wake# od wake this signal is driven to zero when it receives a wake-up packet and either the pme enable bit of the power management control/status register is set to 1b or the advanced power management enabled bit of the wake up control register equals 1b. aux_ present (aux_pwr) 1 1. this signal is used in all three devices and has the same functionality but is denoted as aux_present in the 82573e/v and aux_pwr in the 82573l. i auxiliary power present aux_present must be pulled up to 3.3v standby power if the 82573 is powered from standby supplies. this signal must be pulled down if auxiliary power is not used. clkreq# (82573l only) od clock request . the clock request (clkreq#) signal is located at ball p9 of the 82573l. when it is sampled high, this open-drain signal alerts the system that the 82573l does not need the pcie* differential reference clock. during normal operation, the 82573l keeps clkreq# asserted (low), and the system supplies this clock to the device on the pe_clkp and pe_clkn signals. the 82573l deasserts clkreq# (high) when it is in an electrical idle state (l1 and l2 ), and the system might choose to continue supplying the reference clock or gate it conserving platform power. the clkreq# signal should be connected to the clock driver that supplies the 82573l pcie* clock. if other devices use the same clkreq# signal, a pull-up resistor should be used to ensure that no device pulls this signal low when it is powered off. name definition
82573?datasheet 12 2.4 non-volatile memory interface signals 2.5 miscellaneous signals 2.5.1 reset and power-down signals signal type name and function nvm_si i/o nvm serial data output the data output pin is used for input to th e non-volatile memory device. this pin is occasionally used as input during arbitration. this signal has an internal pull-up resistor. nvm_so i nvm serial data input the data input pin is used for output from the non-volatile memory device to the 82573. this signal has an internal pull-up resistor. nvm_sk o ts nvm serial clock the serial clock provides the clock rate for the memory interface. nvm_cs# i/o nvm chip enable this signal is used to enable the device. th is signal has an internal pull-up resistor. nvm_req o nvm arbitration request. this signal is used to request use of the nvm interface. nvm_prot i/pu nvm protection enable. this pin should be connected to ground to disable nvm protection; otherwise, nvm protection is enabled. this signal has an internal pull-up resistor. nvm_type i/pu nvm device type if the device uses a flash, this pin should be connected to a pull-down resistor. if the 82573 is connected to an eeprom, this pin can be connected to an external pull-up resistor. this signal has an internal pull-up resistor of 30 k ? 50%. nvm_shared# i/pu nvm shared enable this pin should be connected to a pull-down resistor to enable sharing of spi flash with ich. this signal has an internal pull-up resistor. signal type name and function lan_pwr_ good i lan power good this signal indicates that stable power is available to the 82573. when the signal is low, lan_pwr_good acts as a master reset of the entire device. lan_pwr_good should be connected to a power supervisor driven from auxiliary power. the signal should go active approximately 80 ms after all power rails are within their operating ranges. a pcie* reset must only occur after lan power good is active. device_off# i device off this asynchronously disables the 82573, including voltage regulator control outputs if selected in external control.
13 datasheet?82573 2.5.2 system management bus (smbus) signals 1 note: the signals listed in the following table should not be connected when using an 82573l. refer to the 82573/82562 dual footprint design guide reference schematics for more information. 2.5.3 led signals 2.5.4 other signals 1. the 82573l does not support the system management bus (smbus). signal type name and function smb_clk i/o smbus clock the smbus clock signal is an open drain signal for the serial smbus interface. smb_dat i/o smbus data the smb data signal is an open drain signal for the serial smbus interface. smb_alrt#/ asf_pwr_ good i/o smbus alert/pci power good the smbus alert signal is an open drain si gnal for serial smbus interface. in asf mode, this signal acts as the pci power good input signal. signal type name and function led0# o led0 this pin provides a signal for programmable led indication. led1# o led1 this pin provides a signal for programmable led indication. led2# o led2 this pin provides a signal for programmable led indication. signal type name and function thermn thermp o thermal test pins these pins are used for thermal testing. they can be connected to test points. fusev p fuse supply this should be connected to 2.5v for normal operation.
82573?datasheet 14 2.6 phy analog and crystal signals signal type name and function mdi0n mdi0p a media dependent interface [0] 1000base-t: in mdi configuration, mdip0/mdin0 corresponds to bi_da+/-, and in mdi-x configuration, mdip0/mdin0 corresponds to bi_db+/-. 100base-tx: in mdi configuration, mdip0/mdin0 is used for the transmit pair, and in mdi-x configuration, mdip0/mdin0 is used for the receive pair. 10base-t: in mdi configuration, mdip0/mdin0 is used for the transmit pair, and in mdi-x configuration, mdip0/mdin0 is used for the receive pair. mdi1n mdi1p a media dependent interface [1] 1000base-t: in mdi configuration, mdip1/mdin1 corresponds to bi_db+/-, and in mdi-x configuration, mdip1/mdin1 corresponds to bi_da+/-. 100base-tx: in mdi configuration, mdip1/mdin1 is used for the receive pair, and in mdi-x configuration, mdip1/mdin1 is used for the transmit pair. 10base-t: in mdi configuration, mdip1/mdin1 is used for the receive pair, and in mdi-x configuration, mdip1/mdin1 is used for the transmit pair. mdi2n mdi2p a media dependent interface [2] 1000base-t: in mdi configuration, mdip2/mdin2 corresponds to bi_dc+/-, and in mdi-x configuration, mdip2/mdin2 corresponds to bi_dd+/-. 100base-tx: unused. 10base-t: unused. mdi3n mdi3p a media dependent interface [3] 1000base-t: in mdi configuration, mdip3/mdin3 corresponds to bi_dd+/-, and in mdi-x configuration, mdip3/mdin3 corresponds to bi_dc+/-. 100base-tx: unused. 10base-t: unused. phy_ref a reference input this signal is used as the analog reference input for the phy. it should be connected to a pull-down, 4.99 k ? , 1% resistor. xtal1 i crystal one the crystal one pin is a 25 mhz input signal. it should be connected to a parallel resonant crystal with a frequency tolerance of 30 ppm. the other end of the crystal should be connected to xtal2. xtal2 o crystal two crystal two is the output of an internal oscillator circuit used to drive a crystal into oscillation.
15 datasheet?82573 2.7 test signals 2.7.1 mac test signals 2.7.2 phy test signals 2.7.3 other test signals signal type name and function test_en i factory test pin a 1 k ? pull-down resistor should be attached to ground from this pin for normal operation. alt_clk125 nc alternate 125 mhz clock this signal should not be connected. this signal has an internal pull-up resistor. jtag_tck i jtag test access port clock this signal has an internal pull-down resistor. jtag_tdi i jtag test access port test data in this signal has an internal pull-up resistor. jtag_tdo o/od jtag test access port test data out jtag_tms i jtag test access port mode select this signal has an internal pull-up resistor. clk_view nc clock view the clock view signal is an output for the clock signals required for ieee testing. this signal has an internal pull-up resistor. test[16:0] for the 82573e/v test[10:0] for the 82573l rsvd test pin[16:0] these test pins are for the 82573e/v only. these signals have internal pull-up resistor. for normal operation, these pins should be left unconnected. test pin[10:0] these test pins are for the 82573l only. these signals have internal pull-up resistor. for normal operation, these pins should be left unconnected. signal type name and function phy_hsdacn phy_hsdacp (82573e/v) phy_testn phy_testp (82573l only) 1 1. these signals are used in all three devices and have the same functionality but are denoted as phy_hsdacn and phy_hsdacp in the 82573e/v and ph y_testn and phy_testp in the 82573l. a(out) phy differential test port these signals are used for factory test purposes only. phy_tstpt phy test port this signal is used for factory test purposes only. this pin must be left unconnected for normal operation. signal type name and function sdp[3:0] nc these signals are used for factory test purposes only and have internal pull-up resistors.
82573?datasheet 16 2.8 power signals 2.8.1 power support signals 2.8.2 digital and analog power supply signals 2.9 grounds and no connects signal type name and function ctrl_25 p 2.5v control this is the voltage control signal for external 2.5v. it is only active when the en25reg signal is low (disabled). when external 2.5v and 1.2v supplies are used, ctrl_25 can be left floating or can be connected to ground through a 3.3 k ? resistor. ctrl_12 p 1.2v control this is the voltage control signal for external 1.2v. when external 2.5v and 1.2v supplies are used, ctrl_12 can be left floating or can be connected to ground through a 3.3 k ? resistor. en25reg i/pu enable 2.5v regulator when this signal is high, the internal 2.5v regulator is enabled. when it is low, the internal 2.5v regulator is disables and the ctrl_25 signal is active. this signal should be pulled up to the 3.3v power rail. signal type name and function vcc33 p 3.3v power supply this signal is used for i/o circuits. vcc25 p 2.5v analog power supply these signals are used for phy analog, phy i/o, pcie* analog and phase lock loop circuits. all 2.5v pins should be connected to a single power supply. vcc12 p 1.2v digital power supply these signals are used for core digital, ph y digital, pcie* digital and clock circuits. all 1.2v pins should be connected to a single power supply. ireg25_in (82573e/v) vcc3.3_reg25 (82573l only) 1 1. this signal is used in all three devices and has the same functionality but is denoted as ireg25_in for the 82573e/v and vcc3.3_reg25 for the 82573l. p ireg25_in 3.3v power supply for internal 2.5v regu lator. when external 2.5v and 1.2v supplies are used, ireg25_in should be connected to 3.3v. vcc25_out p vcc25_out 2.5v output supply from internal powe r supply. when external 2.5v and 1.2v supplies are used, vcc25_out can be left floating. signal type name and function vss p ground these signals connect to ground. vss is also referred to as gnd. nc no connect these pins are reserved by intel and might have factory test functions. for normal operation, do not connect any circuitry to these pins. do not connect pull-up or pull-down resistors.
17 datasheet?82573 3.0 voltage, temperature, and timing specifications 3.1 absolute maximum ratings 3.2 recommended operating conditions 3.3 power supply connections there are three options in providing power to the 82573: ? connecting the 82573 to three external power supplies with nominal voltages of 3.3v, 2.5v, and 1.2v. this is covered in section 3.3.1 . ? powering the 82573 with only an external 3.3v supply and using internal power regulators from the 82573 combined with external pnp transistors to supply the 2.5v and 1.2v levels. this is covered in section 3.3.3 . ? using the 2.5v internal (on-die) regulator combined with an external pnp transistor to supply the 1.2v level. this is covered in section 3.3.3 . table 1. absolute maximum ratings 1 1. maximum ratings are referenced to ground (vss). permanent device damage is likely to occur if the ratings in this table are exceeded for an indefinite duration. these values should not be used as the limits for normal device operations. this specification is not guaranteed by design or simulations. symbol parameter min max unit tstg storage temperature -40 125 c vcc (3.3) dc supply voltage on 3.3v pins with respect to vss -0.3 6.6 v vcc (2.5) dc supply voltage on 2.5v pins with respect to vss 2 2. during normal device power up and power down, the 2.5v and 1.2v supplies must not ramp before the 3.3v. -0.3 5.0 v vcc (1.2) dc supply voltage on 1.2v pins with respect to vss b -0.3 2.4 v vin input voltage (digital inputs) -1.0 vcc (3.3) + 0.3 (less than 6.6 v) v avin analog input voltage (digital inputs) -1.0 vcc (2.5) + 0.3 (less than 5.0 v) v r pud pull-up/pull-down resistor value 15 50 k ? table 2. recommended operating conditions symbol parameter condition min typical max units t op operating temperature with external regulators 070c operating temperature with on-die 2.5v regulator 055c v perif periphery voltage range 3.3 v 3% 3.0 3.3 3.6 v v d core digital voltage range 1.2 v 5% 1.14 1.2 1.26 v v a analog vdd range 2.5 v 5% 2.375 2.5 2.625 v
82573?datasheet 18 3.3.1 external lvr power delivery the following power supply requirements apply to designs where the 82573 is supplied by external voltage regulators. these systems do not use the internal regulator logic built into the 82573 as described in section 3.3.3 . table 3. 3.3v external supply voltage ramp and sequencing recommendations parameter description min max unit rise time rise time from 10% to 90% 5 100 1 ms monotonicity voltage dip allowed in ramp 300 mv slope ramp rate at any time between 10% to 90% minimum = (0.8 * vmin) / (maximum rise time) maximum = (0.8 * vmax) / (minimum rise time) 1500 mv/ms operational range voltage range for normal operating conditions 3 3.6 v ripple maximum voltage ripple at a bandwidth of 50 mhz 100 mv pk-pk overshoot maximum voltage allowed 2 660 mv capacitance minimum capacitance 25 f 1. good design practices achieve voltage ramps to within the regulation bands in ap proximately 20 ms or less. 2. excessive overshoot can affect long term reliability. table 4. 2.5v external supply voltage ramp and sequencing recommendations parameter description min max unit rise time rise time from 10% to 90% 2.5 100 1 ms monotonicity voltage dip allowed in ramp 200 mv slope ramp rate at any time between 10% to 90% minimum = (0.8 * vmin) / (maximum rise time) maximum = (0.8 * vmax) / (minimum rise time) 1500 mv/ms operational range voltage range for no rmal operating conditions 2.375 2.625 v operational range voltage range for normal operating conditions -5 +5 % ripple maximum voltage ripple at a bandwidth of 50 mhz 60 mv pk-pk undershoot maximum voltage allowed will not exceed 10% of nominal supply overshoot maximum voltage allowed 2 480 mv output capacitance capacitance range when using a pnp circuit 4.7 25 f input capacitance capacitance range when using a pnp circuit 4.7 f capacitance esr equivalent series resistance of output capacitance 3 10 m ? i ctrl maximum output current rating with respect to ctrl_25 20 ma 1. good design practices achieve voltage ramps to within the regulation bands in ap proximately 20 ms or less. 2. excessive overshoot can affect long term reliability. 3. tantalum capacitors must not be used.
19 datasheet?82573 3.3.2 power sequencing with external regulators the following power-on and power-off sequence should be applied when external power supplies are in use. designs must comply with the required power sequence to avoid risk of either latch-up or forward biased internal diodes. generally, the 82573 power sequencing should power up the three power rails in the following order: 3.3v ? 2.5v ? 1.2v. however, if this general guideline is not followed, there are specific requirements that must be adhered to. these requirements are listed in the following two subsections. 3.3.2.1 external lvr power up sequencing and tracking sequencing of the external supplies during power up might be necessary to ensure that the 82573 is not electrically overstressed and does not latch-up. these requirements are shown in figure 2 . the 82573 core voltage (1.2v) cannot exceed the 3.3v supply by more than 0.5 v at any time during the power up. the 82573 core voltage (1.2v) cannot exceed the 2.5v supply by more than 0.5 v at any time during the power up. the core voltage is not required to begin ramping before the 3.3v or the 2.5v supply. the 82573 analog voltage (2.5v) can not exceed the 3.3v supply by more than 0.5 v at any time during the power up. the analog voltage is not required to begin ramping before the 3.3v supply. table 5. 1.2v external supply voltage ramp and sequencing recommendations parameter description min max unit rise time rise time from 10% to 90% 1.5 1 1. good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. ms monotonicity voltage dip allowed in ramp 120 mv slope ramp rate at any time between 10% to 90% minimum = (0.8 * vmin) / (maximum rise time) maximum = (0.8 * vmax) / (minimum rise time) 1500 mv/ms operational range voltage range for no rmal operating conditions 1.14 1.26 v operational range voltage range for normal operating conditions -5 +5 % ripple maximum voltage ripple at a bandwidth of 50 mhz 60 mv pk-pk undershoot maximum voltage allowed will not exceed 10% of nominal supply overshoot maximum voltage allowed 2 2. excessive overshoot can affect long term reliability. 500 mv output capacitance capacitance range when using a pnp circuit 4.7 25 f input capacitance capacitance range when using a pnp circuit 4.7 f capacitance esr equivalent series resistance of output capacitance 3 3. tantalum capacitors must not be used. 10 m ? i ctrl maximum output current rating with respect to ctrl_12 20 ma
82573?datasheet 20 ? if the 1.2v and 2.5v rails power up before 3.3v, they should never exceed the 3.3v supply by more than 0.3 v. ? at power down, all three supplies should be turned off simultaneously. if the 3.3v supply powers down first, the 1.2v and 2.5v supplies must never exceed the 3.3v supply by more than 0.3 v. 3.3.2.2 external lvr power down sequencing there are no specific power down sequencing and tracking requirements for the 82573 silicon. the risk of latch-up or electrical overstress is small since the only charge storing in decoupling capacitors is left in the system. 3.3.3 internally generated power delivery the 82573 has two internal linear voltage regulator controllers. the controllers use external transistors to generate 2 of the 3 required voltages: 2.5v (nominal) and 1.2v (nominal). these two voltages are stepped down from a 3.3v source. figure 2. minimum requirements for power supply sequencing max difference 0.3 v max difference 0.3 v max difference 0.3 v max difference 0.3 v 1.2v (core supply) 2.5v 3.3v 3.3v 2.5v 1.2v (core supply) table 6. 3.3v internal power supply parameters parameter description min max units rise time time from 10% to 90% mark 5 ms monotonicity voltage dip allowed in ramp - 300 mv slope ramp rate at any given time between 10% and 90% min: 0.8*v(min)/rise time (max) max: 0.8*v(max)/rise time (min) - 1500 mv/ms operational range voltage range for normal operating conditions 3.0 3.6 v ripple 1 1. the peak to peak output rippled is measured at 20 mhz bandwidth within the operational range. maximum voltage ripple (peak to peak) - 100 mv overshoot maximum overshoot allowed - 660 mv overshoot settling time maximum overshoot allowed duration. (at that time delta voltage should be lower than 5 mv from steady state voltage) -3ms
21 datasheet?82573 3.3.4 internal lvr power sequencing all supplies should rise monotonically. sequencing of the supplies is controlled by the 82573. 3.3.4.1 power up sequencing and tracking during power up, the sequencing and tracking of the internally controlled supplies (2.5v and 1.2v) are controlled by the 82573. no specific motherboard requirements are necessary to prevent electrical overstress or latch-up. the 82573 analog voltage (2.5v) never exceeds the 3.3v supply at any time during the power up. this is because the 2.5v supply is generated from the 3.3v supply when the internal voltage regulator control logic is being used. figure 3 shows the internal lvr circuit. the 2.5v supply tracks the 3.3v ramp. the 82573 core voltage (1.2v) never exceeds the 3.3v at any time during the power up. this is because the 2.5v supply is generated from the 3.3v supply when the internal voltage regulator control logic is being used. figure 3 shows the internal lvr circuit. the 1.2v ramp is delayed internally to prevent it from exceeding the 2.5v and 3.3v supply at any time. the delay is proportional to the slope of the 3.3v ramp. the delay is approximated by t ramp (3.3v)*0.25 < t delay (1.2v) < t ramp (3.3v)*0.75. t ramp is defined to the ramp rate of the 3.3v input to the internal voltage regulator circuit. ? it is recommended that the voltage on a lower voltage rail never exceed the voltage on a higher voltage rail during power on. ? there are no minimum time requirements between the voltage rails as long as they power up in sequence: 3.3v 2.5v 1.2v. ? all 3 supplies must be stable for at least 80 ms before lan_pwr_good is asserted. 100 ms is preferable if possible. ? a pcie* reset must occur after lan power good is active. 3.3.4.2 internal lvr power down sequencing there are no specific power down sequencing and tracking requirements for the 82573 device. the risk of latch-up or electrical overstress is small because the only charge storing in decoupling capacitors is left in the system. figure 3. power supply sequencing 0 voltage 1.2v 2.5v 3.3v minimum 80 ms time lan_pwr_good
82573?datasheet 22 3.3.4.3 internal voltage regulators components for the 82573 3.3.4.4 2.5v internal lvr specification table 7. 82573 bill of materials (bom) of components for internal regulator description quantity recommended component manufacturer part number package pnp transistor for 1.2v lvr 1 philips bcp-69-16 sot-223 pnp transistor for 2.5v lvr 1 philips bcp-69-16 sot-223 table 8. 2.5v internal lvr specification 1 1. the use of tantalum capacitors is not recommended. parameter value units comments minimum maximum input voltage 3.0 3.6 v input voltage slew rate 5 ms input capacitance 4.7 f input capacitance esr 10 m ? load current 1 - a v out = 2.500 v output voltage tolerance -5 +5 % output capacitance 4.7 f output capacitance esr 10 m ? current consumption during power up 0.5 ma current consumption during power down 0.5 ma maximum undershoot < 10 % of nominal supply peak to peak output ripple 120 mv 60 mv at 20 mhz bandwidth psrr 20 db external pnp h fe 100
23 datasheet?82573 3.3.4.5 1.2v internal lvr specification 3.3.4.6 pnp transistor specification for internal lvr table 9. 1.2v internal lvr specification 1 1. the use of tantalum capacitors is not recommended. parameter value units comments minimum maximu m input voltage 3.0 3.6 v input voltage slew rate 5 ms input capacitance 4.7 f input capacitance esr 10 m ? load current 1 - a v out = 1.200 v output voltage tolerance -5 +5 % output capacitance 4.7 f output capacitance esr 10 m ? current consumption during power up 0.5 ma current consumption during power down 0.5 ma maximum undershoot < 10 % of nominal supply peak to peak output ripple 120 mv 60 mv at 20 mhz bandwidth psrr 20 db external pnp h fe 100 table 10. pnp specification (sheet 1 of 2) symbol description min max units v ce,sat collector-emitter saturation voltage - 0.5 v i c (max) collector current, maximum sustained - 1000 ma i b base current, maximum sustained - 10 ma v be base-emitter on voltage - 1 v t jmax maximum junction temperature - 125 c
82573?datasheet 24 3.3.4.7 internal lvr board schematic when using the internal voltage regulator controllers built into the 82573, resistors might need to be placed in series with the emitter in order to prevent the pnp transistors from overheating. these series resistors dissipate a portion of the power that would otherwise be dissipated by the pnp devices. the value and power rating of the resistors must be carefully chosen to balance thermal limits against the pnp characteristics against total current draw. the regulator must never drop below the minimum v ce and out of the linear region. the effective resistance of the pass resistors should equal approximately 1 ? and have a combined power dissipation rating of 0.5 watts for the 82573. figure 4 shows the recommended implementation. power dissipation maximum total power dissipation - 1.35 w h fe dc current gain 100 - - f t current gain product bandwidth 10 - mhz table 10. pnp specification (sheet 2 of 2) symbol description min max units
25 datasheet?82573 3.4 dc and ac specifications figure 4. 82573 2.5v and 1.2v lvr schematic table 11. 82573e and 82573v maximum measured external power characteristics 1 1. maximum conditions refer to fast silicon, high temperature and nominal vcc. system state link state 82573e power (mw) with intel? amt 82573v power (mw) without intel? amt s0 1000 mbps active (maximum power) 1548 1426 . l 3 7 5 2 8 r o f 1 6 r r o f d e d e e n t o n s i m h o 1 y l n o l 3 7 5 2 8 . d a e t s n i d e s u e b y a m m h o 0 . v 2 . 1 o t y l t c e r i d 9 2 c t c e n n o c can s n g i s e d . l 3 7 5 2 8 r o f 0 6 r r o f d e d e e n t o n s i m h o 1 y l n o l 3 7 5 2 8 . d a e t s n i d e s u e b y a m m h o 0 . v 5 . 2 o t y l t c e r i d 3 2 c t c e n n o c y a m s n g i s e d g n i s u s d n e m m o c e r l e t n i 4 q f o r e t t i m e e h t t a f u 0 4 . l i a r v 3 . 3 e h t n o . s r o t i c a p a c c i m a r e c e s u e c a f r u s k n i s - t a e h s e r i u q e r 4 q . n i m ' ' 5 . 0 x ' ' 5 . 0 f o d a p - t a e h s e r i u q e r 3 q f o d a p e c a f r u s k n i s . n i m ' ' 5 . 0 x ' ' 5 . 0 e h t g n i s u n e h w l l a t s n i e g a t l o v v 5 . 2 d e t a r g e t n i l a n r e t x e h t i w r o t a l u g e r t o n o d . r o t s i s n a r t s s a p die 2.5v - n o f i l l a t s n i g n i s u s d n e m m o c e r l e t n i 3 q f o r e t t i m e e h t t a f u 0 4 . l i a r v 3 . 3 e h t n o . s r o t i c a p a c c i m a r e c e s u 1.2v voltage regulator 2.5v voltage regulator regulator is used.
82573?datasheet 26 table 12. 82573e and 82573v typical measured external power characteristics 1 1. maximum conditions refer to fast silicon, high temperature and nominal vcc. system state link state 3.3v current (ma) 2.5v current (ma) 1.2v current (ma) 82573e/v power (mw) 2 3 2. for 10/100 mb/s non-stress mode with intel? amt, add 12 mw to this number (for example, using ide-r functionality). 3. for 10/100 mb/s stress mode active intel? amt, add 120 mw to this number (for example, using ide-r functionality). s0 1000 mb/s: intel? amt (82573e only) 12 297 551 1443.3 1000 mb/s active 12 297 490 1370.1 1000 mb/s idle 12 276 380 1185.6 100 mb/s active 11 130 144.5 534.7 100 mb/s idle 11 107 101 425 10 mb/s active 7 167 125.5 591.2 10 mb/s idle 7 76 82 311.5 no link (spd) 3 40 73 197.5 sx 100 mb/s idle (wake) 11 104 93.5 408.5 10 mb/s idle (wake) 7 72 74.5 292.5 no link (no wake) 3 36 4 4. the current use is slightly higher in the device off state than in the no link state. this occurs since a phy reset is required in the device off state, which overrides the phy power down. 64.5 177.3 device off 3 42 d 48.5 173.1 table 13. 82573e and 82573v 2.5v internal power regulator numbers system state link state 3.3v current (ma) 2.5v current (ma) (on-die 2.5v regulator) 1.2v current (ma) 82573e/v power (mw) s0 1000 mb/s: active with full management 313 internal 607 1760 1000 mb/s active 313 internal 506 1638 1000 mb/s idle 294 internal 404 1453 100 mb/s active 142 internal 145 642 100 mb/s idle 119 internal 101 513 10 mb/s active 173 internal 126 722 10 mb/s idle 84 internal 83 376 d0 no link (spd) 44 internal 73 233 sx d3 100 mb/s idle (wake) 116 internal 94 493 d3 10 mb/s idle (wake) 80 internal 75 354 d3 no link (no wake) 40 internal 64 209 device off 45 internal 49 207
27 datasheet?82573 table 14. 82573l maximum measured power characteristics 1 1. maximum conditions refer to fast silicon, high temperature and nominal vcc. system state link state 82573l (mw) s0 1000 mb/s active (maximum power) 1296 table 15. 82573l measured power characteristics system state link state 3.3v current (ma) 2.5v current (ma) 1.2v current (ma) 82573l power (mw) s0 1000 mb/s active 14.8 288.5 372.5 1217 1000 mb/s idle 14.8 243.2 294.0 1010 100 mb/s active 14.0 121.3 111.5 483 100 mb/s idle 14.2 78.8 58.5 314 10 mb/s active 10.5 169 118 504 10 mb/s idle 10.3 143.5 91.8 194 d0 no link (spd) 6.2 7.0 12.3 53 sx d3 100 mb/s idle (wake) 14.2 78.8 49.3 303 d3 10 mb/s idle (wake) 10.5 45.7 31.0 186 d3 no link (no wake) 6.2 7.3 12.2 53 table 16. dc specifications symbol parameter condition min max unit vih input high voltage 2.0 v vil input low voltage 0.8 v vhy input hysteresis 100 mv voh output high voltage 2.4 v vol output low voltage 0.4 v ilkg input leakage current 0 < vin < vccp 50 a rpup/ rpdn internal pull up and pull down resistor 15 50 k ? cin/out pin capacitance input and bi-directional buffer 2.5 pf cout output pin capacitance output only buffer 2.0 pf
82573?datasheet 28 3.5 external interfaces 3.5.1 crystal the quartz crystal is strongly recommended as a low cost and high performance choice with the 82573 device. quartz crystals are the mainstay of frequency control components and are available from numerous vendors in many package types with various specification options. 3.5.2 external clock oscillator if an external oscillator is used to provide a clock to the 82573, the connection shown in the figure below must be used. the xtal2 output signal of the 82573 must not be connected. the xtal1 input signal receives the output of the oscillator directly. ac coupling is not recommended. table 17. led dc specifications symbol parameter 1 1. outputs are inputs/outputs in test mode. condition min max unit voh output high voltage at 12 ma 2.4 v vol output low voltage at 12 ma 0.4 v ioz 3-state output leakage current voh = vdd or vss 10 mv ios output short current vdd = 3.6 v, vo = vdd, vdd = 3.6 v, vo = vss a cin/out pin capacitance 2 2. this parameter is characterized but not tested. input and bi-directional buffer 2.5 pf table 18. crystal specifications parameter name symbol recommended value max/min range conditions frequency f o 25.000 mhz - at 25 c vibration mode - fundamental - - frequency tolerance ? f/f o at 25 c 30 ppm at 25 c temperature tolerance ? f/f o 30 ppm - operating temperature t opr 0 c to +70 c - equivalent series resistance (esr) r s 40 ? 50 ? (max) at 25 mhz load capacitance c load 20 pf - shunt capacitance c o 6 pf - max drive level dl 500 w 1 mw - nominal drive level dl 200 w 500 w - aging f/f o 5 ppm per year 5 ppm per year - board capacitance c s 4 pf 1 1. this value can change up to 10%. - external capacitors c1, c2 22 pf - board resistance r s 0.1 ? 1 ? -
29 datasheet?82573 3.5.3 non-volatile memory (nvm) interface: eeprom figure 5. external clock oscillator connectivity to the 82573 table 19. specification for external clock oscillator parameter name symbol value conditions frequency f o 25.0 mhz at 25 c swing v p-p 3.3 0.3 v - frequency tolerance ? f/f o 30 ppm 0 c to +70 c operating temperature t opr -20 c to +70 c 0 c to +70 c aging ? f/f o 5 ppm per year - table 20. nvm interface timing specifications for eeprom (sheet 1 of 2) symbol parameter min typ max units t sck sck clock frequency 022.1mhz t ru input rise time 2.5 2 s t fi input fall time 2.5 2 s t wh sck high time 1 200 250 ns t wh sck low time a 200 250 ns t cs cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns t su data-in setup time 50 ns t h data-in hold time 50 ns t v output valid 0 200 ns 3.3 v 82563eb/82564eb xtal1 xtal2 82573
82573?datasheet 30 4.0 package and pinout information this section describes the 82573 physical characteristics and pin-to-signal mapping. 4.1 package information the 82573 device is a lead-free 196-pin thin and fine pitch ball grid array (tf-bga) measuring 15 mm by 15 mm. the no minal ball pitch is 1.0 mm. t ho output hold time 0ns t dis output disable time 250 ns t wc write cycle time 10 ms 1. 50% duty cycle. table 20. nvm interface timing specifications for eeprom (sheet 2 of 2) symbol parameter min typ max units figure 6. 82573 controller tf-bga package ball pad dimensions 0.4 mm solder resist opening 0.55 mm metal diameter detail area
31 datasheet?82573 figure 7. 82573 mechanical specifications
82573?datasheet 32 4.2 thermal specifications the case temperature (t c ) is calculated using the equation: t c = t a + p ( ? ja - ? jc ) junction temperature (t j ) is calculated using the equation: t j = t a + p ? ja the power consumption (p) is calculated by using the typical icc and nominal vcc where t a represents the ambient temperature. the thermal resistances are listed in ta b l e 2 1 .
33 datasheet?82573 thermal resistances are determined empirically with test devices mounted on standard thermal test boards. real system designs may have different characteristics due to board thickness, arrangement of ground pl anes, and proximity of other components. the case temperature measurements should be used to assure that the 82573 is operating under recommended conditions. the use of a heat sink device is not required. 4.3 pinout information 4.3.1 pcie bus interface signals table 21. thermal resistance values symbol parameter value at specified airflow (m/s) units 0123 tj maximum junction temperature 127.1 122.1 119.3 117.5 c ? ja thermal resistance, junction-to- ambient 26.0 23.7 22.4 21.6 c/watt ? jc thermal resistance, junction-to- case 6.1 6.1 6.1 6.1 c/watt table 22. pcie data signals signal pin signal pin signal pin pe_clkn g2 pe_t0n c1 pe_r0n f1 pe_clkp g1 pe_t0p d1 pe_r0p f2
82573?datasheet 34 4.3.2 non-volatile memo ry interface signals 4.3.3 miscellaneous signals table 23. pci express miscellaneous signals signal pin signal pin signal pin pe_rst# p7 pe_wake# p10 aux_present (82573e/v) / aux_pwr (82573l) 1 1. this signal is used in all three devices and has the same functionality but is denoted as aux_present in the 82573e/v or aux_pwr in the 82573l. c6 clkreq# (82573l only) p9 table 24. non-volatile memory interface signals signal pin signal pin signal pin nvm_si a9 nvm_cs# b10 nvm_type a6 nvm_so b9 nvm_req b4 nvm_shared# d3 nvm_sk c9 nvm_prot a5 table 25. reset and power-down signals signal pin signal pin signal pin lan_pwr_good p5 device_off# l7 table 26. smbus signals signal pin signal pin signal pin smb_clk p11 smb_dat m11 smb_alrt#/ asf_pwr_ good n11 table 27. led signals signal pin signal pin signal pin led0# b11 led1# c11 led2# a12 table 28. other signals signal pin signal pin signal pin thermn l2 thermp l3
35 datasheet?82573 4.3.4 phy signals 4.3.5 test signals table 29. analog and crystal signals signal pin signal pin signal pin mdi0n c14 mdi2n f14 phy_ref d12 mdi0p c13 mdi2p f13 xtal1 k14 mdi1n e14 mdi3n h14 xtal2 j14 mdi1p e13 mdi3p h13 table 30. 82573e/v mac test signals 1 1. these test signals do not apply to the 82573l. signal pin signal pin signal pin test_en a13 test1 h2 test9 m3 alt_clk125 n10 testpt2 h3 test10 n2 jtag_tck n5 testpt3 j1 test11 p1 jtag_tdi p4 testpt4 j2 test12 n3 jtag_tdo p6 test5 j3 test13 m8 jtag_tms n4 test6 k1 test14 (82573e/v only) p9 clk_view l14 test7 l1 test15 (82573e/v only) e3 test0 h1 test8 m1 test16 (82573e/v only) a14 table 31. 82573l mac test signals 1 1. these test signals do not apply to the 82573e or 82573v devices. signal pin signal pin signal pin test_en a13 clk_view l14 test5 j3 alt_clk125 n10 test0 h1 test6 k1 jtag_tck n5 test1 h2 test7 l1 jtag_tdi p4 testpt2 h3 test8 m1 jtag_tdo p6 testpt3 j1 test9 m3 jtag_tms n4 testpt4 j2 table 32. phy test interface signals signal pin signal pin signal pin phy_hsdacn b13 phy_hsdacp b12 phy_tstpt b14
82573?datasheet 36 4.3.6 power supply signals table 33. 82573e/v other test signals 1 1. these test signals do not apply to the 82573l. signal pin signal pin signal pin sdp[0] a8 sdp[1] b8 sdp[2] c8 sdp[3] c7 table 34. power support signals signal pin signal pin signal pin ctrl_25 a4 ctrl_12 p3 en25reg b5 table 35. power signals signal pin signal pin signal pin vcc33 a7 vcc25 j12 vcc12 j6 vcc33 d9 vcc25 k13 vcc12 j7 vcc33 f3 vcc25 l12 vcc12 j8 vcc33 j4 vcc25 m4 vcc12 j9 vcc33 m10 vcc25 n7 vcc12 j10 vcc33 n6 vcc25_out b1 vcc12 j11 vcc33 n8 vcc25_out b2 vcc12 k3 vcc33 p2 vcc12 a10 vcc12 k4 vcc33 p12 vcc12 c4 vcc12 k5 ireg25_in a2 vcc12 c5 vcc12 k6 ireg25_in a3 vcc12 f12 vcc12 k7 fusev m2 vcc12 g6 vcc12 k8 vcc25 a11 vcc12 g12 vcc12 k9 vcc25 b6 vcc12 g13 vcc12 k10 vcc25 g3 vcc12 h6 vcc12 k11 vcc25 g5 vcc12 h7 vcc12 l5 vcc25 h4 vcc12 h8 vcc12 l9 vcc25 h5 vcc12 h11 vcc12 l10 vcc25 j5 vcc12 h12
37 datasheet?82573 table 36. ground signals signal pin signal pin signal pin vss a1 vss e5 vss g4 vss b3 vss e6 vss g7 vss c2 vss e7 vss g8 vss c10 vss e8 vss g9 vss c12 vss e9 vss g10 vss d2 vss e10 vss g11 vss d4 vss f4 vss g14 vss d5 vss f5 vss h9 vss d6 vss f6 vss h10 vss d7 vss f7 vss k2 vss d8 vss f8 vss n1 vss d13 vss f9 vss n12 vss e2 vss f10 vss p8 vss e4 vss f11 table 37. 82573e/v no connect signals 1 1. these test signals do not apply to the 82573l. signal pin signal pin signal pin nc b7 nc k12 nc m9 nc c3 nc l4 nc m12 ncd10ncl6ncm13 ncd11ncl8ncm14 nc d14 nc l11 nc n9 nc e1 nc l13 nc n13 nce11ncm5ncn14 nce12ncm6ncp13 ncj13ncm7ncp14 table 38. 82573l no connect signals 1 (sheet 1 of 2) signal pin signal pin signal pin nc a8 nc e12 nc m9 nc a14 nc j13 nc m12 nc b7 nc k12 nc m13 nc b8 nc l4 nc m14 nc c3 nc l6 nc n2 nc c7 nc l8 nc n3 nc c8 nc l11 nc n9 nc d10 nc l13 nc n13
82573?datasheet 38 4.4 visual pin assignments figure 8. 82573e and 82573v gigabit ethernet controller pinout ncd11ncm5ncn14 ncd14ncm6ncp1 nc e1 nc m7 nc p13 nc e3 nc m8 nc p14 nc e11 1. these test signals do not apply to the 82573e or 82573v devices. table 38. 82573l no connect signals 1 (sheet 2 of 2) signal pin signal pin signal pin vcc25_ out pe_t0n pe_tr0p nc pe_r0n pe_clkp test0 test3 test11 vss test8 test7 test6 vss vcc25_ out vss vss vss pe_r0p pe_clkn test1 test4 vcc33 test10 fusev thermn vss ireg25_in vss nc nvm_ shared test15 vcc33 vcc25 test2 test5 ctrl_12 test12 test9 thermp vcc12 ireg25_in nvm_req vcc12 vss vss vss vss vcc25 vcc33 jtag_tdi jtag_tms vcc25 nc vcc12 ctrl_25 en25reg vcc12 vss vss vss vcc25 vcc25 vcc25 lan_pwr_ good jtag_ tck nc vcc12 vcc12 nvm_ prot vcc25 aux_ present vss vss vss vcc12 vcc12 vcc12 jtag_tdo vcc33 nc nc vcc12 nvm_ type nc sdp[3] vss vss vss vss vcc12 vcc12 pe_rst# vcc25 nc device_ off# vcc12 vcc33 sdp[1] sdp[2] vss vss vss vss vcc12 vcc12 vss vcc33 test13 nc vcc12 sdp[0] nvm_so vcc33 vss vss vss vss vcc12 test14 nc nc vcc12 vcc12 nvm_si vss nc vss vss vss vss vcc12 alt_clk125 vcc33 vcc12 vcc12 led0# led1# nc nc vss vss vcc12 vcc12 smb_clk smb_alrt#/ asf_pwr_ good smb_dat nc vcc12 vcc25 phy_ hsdacp vss phy_ref nc vcc12 vcc12 vcc12 vcc25 vcc33 vss nc vcc25 nc led2# mdi0p vss mdi1p mdi2p vcc12 mdi3p nc nc nc nc nc vcc25 test_en mdi0n nc mdi1n mdi2n vss mdi3n xtal2 nc nc nc clk_view xtal1 test16 abcde fghj kl m np 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcc12 nvm_cs# nvm_sk pe_wake# phy_ hsdacn phy_ tstpt
39 datasheet?82573 figure 9. 82573l gigabit ethernet controller pinout vcc25_ out pe_t0n pe_tr0p nc pe_r0n pe_clkp test0 test3 nc vss test8 test7 test6 vss vcc25_ out vss vss vss pe_r0p pe_clkn test1 test4 vcc33 test10 fusev thermn vss vcc3.3_ reg25 vss nc nvm_ shared nc vcc33 vcc25 test2 test5 ctrl_12 nc test9 thermp vcc12 vcc3.3_ reg25 nvm_req vcc12 vss vss vss vss vcc25 vcc33 jtag_tdi jtag_tms vcc25 nc vcc12 ctrl_25 en25reg vcc12 vss vss vss vcc25 vcc25 vcc25 lan_pwr_ good jtag_ tck nc vcc12 vcc12 nvm_ prot vcc25 aux_pwr vss vss vss vcc12 vcc12 vcc12 jtag_tdo vcc33 nc nc vcc12 nvm_ type nc nc vss vss vss vss vcc12 vcc12 pe_rst# vcc25 nc device_ off# vcc12 vcc33 nc nc vss vss vss vss vcc12 vcc12 vss vcc33 nc nc vcc12 nc nvm_so vcc33 vss vss vss vss vcc12 clk_req# nc nc vcc12 vcc12 nvm_si vss nc vss vss vss vss vcc12 alt_clk125 vcc33 vcc12 vcc12 led0# led1# nc nc vss vss vcc12 vcc12 rsvd rsvd rsvd nc vcc12 vcc25 phy_ hsdacp vss phy_ref nc vcc12 vcc12 vcc12 vcc25 vcc33 vss nc vcc25 nc led2# mdi0p vss mdi1p mdi2p vcc12 mdi3p nc nc nc nc nc vcc25 test_en mdi0n nc mdi1n mdi2n vss mdi3n xtal2 nc nc nc clk_view xtal1 nc abcde fghj kl m np 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcc12 nvm_cs# nvm_sk pe_wake# phy_ hsdacn phy_ tstpt

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